High power MOS transistors are produced by connecting in parallel, sub transistors, each of which is designed for a smaller power. By connecting the source, drain and gate terminals of the sub transistors in parallel, the high power MOS transistor behaves in an application circuit, like a component with the three usual terminals, i.e. a source terminal, a drain terminal and a gate terminal.
FIG. 2 shows how, according to the state of the art, sub transistors are connected in parallel to form a high power MOS transistor. This figure only shows six sub transistors T1 to T6, although a high power MOS transistor can be made up of a significantly larger number of sub transistors.
As a result of the manufacturing process in each connection to a gate terminal, a resistor R1 to R6 exists, which is formed by the resistance of the gate material which consists of polycrystalline silicon. Between the appropriate gate terminal and the relevant source terminal there is also a capacitor CGS1 to CGS6, which is shown in FIG. 2 for clarification. If a forward voltage is applied to the gate terminal G of such a power MOS transistor, then not all the sub transistors switch over to the on-state simultaneously, because the bias voltage reaches the gate electrode of the successive sub transistors via the delay line formed by the resistors R1 to R6 and the capacitors CGS1 to CGS6 delayed by a time constant resulting from a gate resistor and a gate source capacitance, with the result that the leading edge of a signal formed by the power MOS transistor is flattened out. Turning off the power MOS transistor can also not be carried out with a steep edge, but the result is a flattened turning off edge. This delayed turning on and off of the power MOS transistor may be desirable for certain applications but it represents a limitation which is annoying if steep turn-on and turn-off edges are to be obtained. Especially if, for example, a load controlled by the power MOS transistor is to be switched very quickly into the off-state, then it is not possible to achieve such rapid switching off because of the delay mentioned.
A further drawback of the power MOS transistor shown in FIG. 2 consists in the fact that it becomes totally unusable if the gate oxide breaks down at one transistor thus generating a short-circuit.